syscfg

package
v0.0.0-...-3d984ba Latest Latest
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This package is not in the latest version of its module.

 Go to latest Published: Nov 29, 2018 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package syscfg provides interface to SysTem Configuration.

Peripheral: SYSCFG_Periph SysTem Configuration. Instances: 

SYSCFG  mmap.SYSCFG_BASE

Registers: 

0x00 32  CFGR1     Configuration register 1.
0x08 32  EXTICR[4] External interrupt configuration register.
0x18 32  CFGR2     Configuration register 2.

Import: 

stm32/o/f030x8/mmap

Index

Constants

View Source 
const (
	MEM_MODEn    = 0
	DMA_RMPn     = 8
	I2C_FMP_PB6n = 16
	I2C_FMP_PB7n = 17
	I2C_FMP_PB8n = 18
	I2C_FMP_PB9n = 19
)
View Source 
const (
	EXTI0n = 0
	EXTI1n = 4
	EXTI2n = 8
	EXTI3n = 12
)
View Source 
const (
	LOCKUP_LOCKn      = 0
	SRAM_PARITY_LOCKn = 1
	SRAM_PEFn         = 8
)

Variables

View Source 
var SYSCFG = (*SYSCFG_Periph)(unsafe.Pointer(uintptr(mmap.SYSCFG_BASE)))

Functions

This section is empty.

Types

type CFGR1 

type CFGR1 uint32
const (
	MEM_MODE         CFGR1 = 0x03 << 0  //+ SYSCFG_Memory Remap Config.
	DMA_RMP          CFGR1 = 0x1F << 8  //+ DMA remap mask.
	ADC_DMA_RMP      CFGR1 = 0x01 << 8  //  ADC DMA remap.
	USART1TX_DMA_RMP CFGR1 = 0x02 << 8  //  USART1 TX DMA remap.
	USART1RX_DMA_RMP CFGR1 = 0x04 << 8  //  USART1 RX DMA remap.
	TIM16_DMA_RMP    CFGR1 = 0x08 << 8  //  Timer 16 DMA remap.
	TIM17_DMA_RMP    CFGR1 = 0x10 << 8  //  Timer 17 DMA remap.
	I2C_FMP_PB6      CFGR1 = 0x01 << 16 //+ I2C PB6 Fast mode plus.
	I2C_FMP_PB7      CFGR1 = 0x01 << 17 //+ I2C PB7 Fast mode plus.
	I2C_FMP_PB8      CFGR1 = 0x01 << 18 //+ I2C PB8 Fast mode plus.
	I2C_FMP_PB9      CFGR1 = 0x01 << 19 //+ I2C PB9 Fast mode plus.
)

func (CFGR1) Field 

func (b CFGR1) Field(mask CFGR1) int

func (CFGR1) J 

func (mask CFGR1) J(v int) CFGR1

type CFGR2 

type CFGR2 uint32
const (
	LOCKUP_LOCK      CFGR2 = 0x01 << 0 //+ Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1.
	SRAM_PARITY_LOCK CFGR2 = 0x01 << 1 //+ Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1.
	SRAM_PEF         CFGR2 = 0x01 << 8 //+ SRAM Parity error flag.
)

func (CFGR2) Field 

func (b CFGR2) Field(mask CFGR2) int

func (CFGR2) J 

func (mask CFGR2) J(v int) CFGR2

type EXTICR 

type EXTICR uint32
const (
	EXTI0    EXTICR = 0x0F << 0  //+ EXTI 0 configuration.
	EXTI1    EXTICR = 0x0F << 4  //+ EXTI 1 configuration.
	EXTI2    EXTICR = 0x0F << 8  //+ EXTI 2 configuration.
	EXTI3    EXTICR = 0x0F << 12 //+ EXTI 3 configuration.
	EXTI0_PA EXTICR = 0x00 << 12 //  PA[0] pin.
	EXTI0_PB EXTICR = 0x01 << 0  //  PB[0] pin.
	EXTI0_PC EXTICR = 0x02 << 0  //  PC[0] pin.
	EXTI0_PD EXTICR = 0x03 << 0  //  PD[0] pin.
	EXTI0_PF EXTICR = 0x05 << 0  //  PF[0] pin.
	EXTI1_PA EXTICR = 0x00 << 12 //  PA[1] pin.
	EXTI1_PB EXTICR = 0x01 << 4  //  PB[1] pin.
	EXTI1_PC EXTICR = 0x02 << 4  //  PC[1] pin.
	EXTI1_PD EXTICR = 0x03 << 4  //  PD[1] pin.
	EXTI1_PF EXTICR = 0x05 << 4  //  PF[1] pin.
	EXTI2_PA EXTICR = 0x00 << 12 //  PA[2] pin.
	EXTI2_PB EXTICR = 0x01 << 8  //  PB[2] pin.
	EXTI2_PC EXTICR = 0x02 << 8  //  PC[2] pin.
	EXTI2_PD EXTICR = 0x03 << 8  //  PD[2] pin.
	EXTI2_PF EXTICR = 0x05 << 8  //  PF[2] pin.
	EXTI3_PA EXTICR = 0x00 << 12 //  PA[3] pin.
	EXTI3_PB EXTICR = 0x01 << 12 //  PB[3] pin.
	EXTI3_PC EXTICR = 0x02 << 12 //  PC[3] pin.
	EXTI3_PD EXTICR = 0x03 << 12 //  PD[3] pin.
	EXTI3_PF EXTICR = 0x05 << 12 //  PF[3] pin.
)

func (EXTICR) Field 

func (b EXTICR) Field(mask EXTICR) int

func (EXTICR) J 

func (mask EXTICR) J(v int) EXTICR

type RCFGR1 

type RCFGR1 struct{ mmio.U32 }

func (*RCFGR1) AtomicClearBits 

func (r *RCFGR1) AtomicClearBits(mask CFGR1)

func (*RCFGR1) AtomicSetBits 

func (r *RCFGR1) AtomicSetBits(mask CFGR1)

func (*RCFGR1) AtomicStoreBits 

func (r *RCFGR1) AtomicStoreBits(mask, b CFGR1)

func (*RCFGR1) Bits 

func (r *RCFGR1) Bits(mask CFGR1) CFGR1

func (*RCFGR1) ClearBits 

func (r *RCFGR1) ClearBits(mask CFGR1)

func (*RCFGR1) Load 

func (r *RCFGR1) Load() CFGR1

func (*RCFGR1) SetBits 

func (r *RCFGR1) SetBits(mask CFGR1)

func (*RCFGR1) Store 

func (r *RCFGR1) Store(b CFGR1)

func (*RCFGR1) StoreBits 

func (r *RCFGR1) StoreBits(mask, b CFGR1)

type RCFGR2 

type RCFGR2 struct{ mmio.U32 }

func (*RCFGR2) AtomicClearBits 

func (r *RCFGR2) AtomicClearBits(mask CFGR2)

func (*RCFGR2) AtomicSetBits 

func (r *RCFGR2) AtomicSetBits(mask CFGR2)

func (*RCFGR2) AtomicStoreBits 

func (r *RCFGR2) AtomicStoreBits(mask, b CFGR2)

func (*RCFGR2) Bits 

func (r *RCFGR2) Bits(mask CFGR2) CFGR2

func (*RCFGR2) ClearBits 

func (r *RCFGR2) ClearBits(mask CFGR2)

func (*RCFGR2) Load 

func (r *RCFGR2) Load() CFGR2

func (*RCFGR2) SetBits 

func (r *RCFGR2) SetBits(mask CFGR2)

func (*RCFGR2) Store 

func (r *RCFGR2) Store(b CFGR2)

func (*RCFGR2) StoreBits 

func (r *RCFGR2) StoreBits(mask, b CFGR2)

type REXTICR 

type REXTICR struct{ mmio.U32 }

func (*REXTICR) AtomicClearBits 

func (r *REXTICR) AtomicClearBits(mask EXTICR)

func (*REXTICR) AtomicSetBits 

func (r *REXTICR) AtomicSetBits(mask EXTICR)

func (*REXTICR) AtomicStoreBits 

func (r *REXTICR) AtomicStoreBits(mask, b EXTICR)

func (*REXTICR) Bits 

func (r *REXTICR) Bits(mask EXTICR) EXTICR

func (*REXTICR) ClearBits 

func (r *REXTICR) ClearBits(mask EXTICR)

func (*REXTICR) Load 

func (r *REXTICR) Load() EXTICR

func (*REXTICR) SetBits 

func (r *REXTICR) SetBits(mask EXTICR)

func (*REXTICR) Store 

func (r *REXTICR) Store(b EXTICR)

func (*REXTICR) StoreBits 

func (r *REXTICR) StoreBits(mask, b EXTICR)

type RMCFGR1 

type RMCFGR1 struct{ mmio.UM32 }

func (RMCFGR1) Load 

func (rm RMCFGR1) Load() CFGR1

func (RMCFGR1) Store 

func (rm RMCFGR1) Store(b CFGR1)

type RMCFGR2 

type RMCFGR2 struct{ mmio.UM32 }

func (RMCFGR2) Load 

func (rm RMCFGR2) Load() CFGR2

func (RMCFGR2) Store 

func (rm RMCFGR2) Store(b CFGR2)

type RMEXTICR 

type RMEXTICR struct{ mmio.UM32 }

func (RMEXTICR) Load 

func (rm RMEXTICR) Load() EXTICR

func (RMEXTICR) Store 

func (rm RMEXTICR) Store(b EXTICR)

type SYSCFG_Periph 

type SYSCFG_Periph struct {
	CFGR1 RCFGR1

	EXTICR [4]REXTICR
	CFGR2  RCFGR2
	// contains filtered or unexported fields
}

func (*SYSCFG_Periph) BaseAddr 

func (p *SYSCFG_Periph) BaseAddr() uintptr

func (*SYSCFG_Periph) DMA_RMP 

func (p *SYSCFG_Periph) DMA_RMP() RMCFGR1

func (*SYSCFG_Periph) EXTI0 

func (p *SYSCFG_Periph) EXTI0(n int) RMEXTICR

func (*SYSCFG_Periph) EXTI1 

func (p *SYSCFG_Periph) EXTI1(n int) RMEXTICR

func (*SYSCFG_Periph) EXTI2 

func (p *SYSCFG_Periph) EXTI2(n int) RMEXTICR

func (*SYSCFG_Periph) EXTI3 

func (p *SYSCFG_Periph) EXTI3(n int) RMEXTICR

func (*SYSCFG_Periph) I2C_FMP_PB6 

func (p *SYSCFG_Periph) I2C_FMP_PB6() RMCFGR1

func (*SYSCFG_Periph) I2C_FMP_PB7 

func (p *SYSCFG_Periph) I2C_FMP_PB7() RMCFGR1

func (*SYSCFG_Periph) I2C_FMP_PB8 

func (p *SYSCFG_Periph) I2C_FMP_PB8() RMCFGR1

func (*SYSCFG_Periph) I2C_FMP_PB9 

func (p *SYSCFG_Periph) I2C_FMP_PB9() RMCFGR1

func (*SYSCFG_Periph) LOCKUP_LOCK 

func (p *SYSCFG_Periph) LOCKUP_LOCK() RMCFGR2

func (*SYSCFG_Periph) MEM_MODE 

func (p *SYSCFG_Periph) MEM_MODE() RMCFGR1

func (*SYSCFG_Periph) SRAM_PARITY_LOCK 

func (p *SYSCFG_Periph) SRAM_PARITY_LOCK() RMCFGR2

func (*SYSCFG_Periph) SRAM_PEF 

func (p *SYSCFG_Periph) SRAM_PEF() RMCFGR2

Source Files

View all Source files

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