i2c

package
v0.0.0-...-3d984ba Latest Latest
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This package is not in the latest version of its module.

 Go to latest Published: Nov 29, 2018 License: BSD-3-Clause Imports: 4 Imported by: 0

Documentation

Overview

Package i2c provides interface to Inter-integrated Circuit Interface.

Peripheral: I2C_Periph Inter-integrated Circuit Interface. Instances: 

I2C1  mmap.I2C1_BASE
I2C2  mmap.I2C2_BASE

Registers: 

0x00 16  CR1   Control register 1.
0x04 16  CR2   Control register 2.
0x08 16  OAR1  Own address register 1.
0x0C 16  OAR2  Own address register 2.
0x10 16  DR    Data register.
0x14 16  SR1   Status register 1.
0x18 16  SR2   Status register 2.
0x1C 16  CCR   Clock control register.
0x20 16  TRISE TRISE register.

Import: 

stm32/o/l1xx_md/mmap

Index

Constants

View Source 
const (
	PEn        = 0
	SMBUSn     = 1
	SMBTYPEn   = 3
	ENARPn     = 4
	ENPECn     = 5
	ENGCn      = 6
	NOSTRETCHn = 7
	STARTn     = 8
	STOPn      = 9
	ACKn       = 10
	POSn       = 11
	PECn       = 12
	ALERTn     = 13
	SWRSTn     = 15
)
View Source 
const (
	FREQn    = 0
	ITERRENn = 8
	ITEVTENn = 9
	ITBUFENn = 10
	DMAENn   = 11
	LASTn    = 12
)
View Source 
const (
	ADD1_7n  = 1
	ADD8_9n  = 8
	ADD0n    = 0
	ADDMODEn = 15
)
View Source 
const (
	ENDUALn    = 0
	SECADD1_7n = 1
)
View Source 
const (
	SBn       = 0
	ADDRn     = 1
	BTFn      = 2
	ADD10n    = 3
	STOPFn    = 4
	RXNEn     = 6
	TXEn      = 7
	BERRn     = 8
	ARLOn     = 9
	AFn       = 10
	OVRn      = 11
	PECERRn   = 12
	TIMEOUTn  = 14
	SMBALERTn = 15
)
View Source 
const (
	MSLn        = 0
	BUSYn       = 1
	TRAn        = 2
	GENCALLn    = 4
	SMBDEFAULTn = 5
	SMBHOSTn    = 6
	DUALFn      = 7
	PECVALn     = 8
)
View Source 
const (
	CCRVALn = 0
	DUTYn   = 14
	FSn     = 15
)

Variables

View Source 
var I2C1 = (*I2C_Periph)(unsafe.Pointer(uintptr(mmap.I2C1_BASE)))
View Source 
var I2C2 = (*I2C_Periph)(unsafe.Pointer(uintptr(mmap.I2C2_BASE)))

Functions

This section is empty.

Types

type CCR 

type CCR uint16
const (
	CCRVAL CCR = 0xFFF << 0 //+ Clock Control Register in Fast/Standard mode (Master mode).
	DUTY   CCR = 0x01 << 14 //+ Fast Mode Duty Cycle.
	FS     CCR = 0x01 << 15 //+ I2C Master Mode Selection.
)

func (CCR) Field 

func (b CCR) Field(mask CCR) int

func (CCR) J 

func (mask CCR) J(v int) CCR

type CR1 

type CR1 uint16
const (
	PE        CR1 = 0x01 << 0  //+ Peripheral Enable.
	SMBUS     CR1 = 0x01 << 1  //+ SMBus Mode.
	SMBTYPE   CR1 = 0x01 << 3  //+ SMBus Type.
	ENARP     CR1 = 0x01 << 4  //+ ARP Enable.
	ENPEC     CR1 = 0x01 << 5  //+ PEC Enable.
	ENGC      CR1 = 0x01 << 6  //+ General Call Enable.
	NOSTRETCH CR1 = 0x01 << 7  //+ Clock Stretching Disable (Slave mode).
	START     CR1 = 0x01 << 8  //+ Start Generation.
	STOP      CR1 = 0x01 << 9  //+ Stop Generation.
	ACK       CR1 = 0x01 << 10 //+ Acknowledge Enable.
	POS       CR1 = 0x01 << 11 //+ Acknowledge/PEC Position (for data reception).
	PEC       CR1 = 0x01 << 12 //+ Packet Error Checking.
	ALERT     CR1 = 0x01 << 13 //+ SMBus Alert.
	SWRST     CR1 = 0x01 << 15 //+ Software Reset.
)

func (CR1) Field 

func (b CR1) Field(mask CR1) int

func (CR1) J 

func (mask CR1) J(v int) CR1

type CR2 

type CR2 uint16
const (
	FREQ    CR2 = 0x3F << 0  //+ FREQ[5:0] bits (Peripheral Clock Frequency).
	FREQ_0  CR2 = 0x01 << 0  //  Bit 0.
	FREQ_1  CR2 = 0x02 << 0  //  Bit 1.
	FREQ_2  CR2 = 0x04 << 0  //  Bit 2.
	FREQ_3  CR2 = 0x08 << 0  //  Bit 3.
	FREQ_4  CR2 = 0x10 << 0  //  Bit 4.
	FREQ_5  CR2 = 0x20 << 0  //  Bit 5.
	ITERREN CR2 = 0x01 << 8  //+ Error Interrupt Enable.
	ITEVTEN CR2 = 0x01 << 9  //+ Event Interrupt Enable.
	ITBUFEN CR2 = 0x01 << 10 //+ Buffer Interrupt Enable.
	DMAEN   CR2 = 0x01 << 11 //+ DMA Requests Enable.
	LAST    CR2 = 0x01 << 12 //+ DMA Last Transfer.
)

func (CR2) Field 

func (b CR2) Field(mask CR2) int

func (CR2) J 

func (mask CR2) J(v int) CR2

type DR 

type DR uint16

func (DR) Field 

func (b DR) Field(mask DR) int

func (DR) J 

func (mask DR) J(v int) DR

type I2C_Periph 

type I2C_Periph struct {
	CR1 RCR1

	CR2 RCR2

	OAR1 ROAR1

	OAR2 ROAR2

	DR RDR

	SR1 RSR1

	SR2 RSR2

	CCR RCCR

	TRISE RTRISE
	// contains filtered or unexported fields
}

func (*I2C_Periph) ACK 

func (p *I2C_Periph) ACK() RMCR1

func (*I2C_Periph) ADD0 

func (p *I2C_Periph) ADD0() RMOAR1

func (*I2C_Periph) ADD10 

func (p *I2C_Periph) ADD10() RMSR1

func (*I2C_Periph) ADD1_7 

func (p *I2C_Periph) ADD1_7() RMOAR1

func (*I2C_Periph) ADD8_9 

func (p *I2C_Periph) ADD8_9() RMOAR1

func (*I2C_Periph) ADDMODE 

func (p *I2C_Periph) ADDMODE() RMOAR1

func (*I2C_Periph) ADDR 

func (p *I2C_Periph) ADDR() RMSR1

func (*I2C_Periph) AF 

func (p *I2C_Periph) AF() RMSR1

func (*I2C_Periph) ALERT 

func (p *I2C_Periph) ALERT() RMCR1

func (*I2C_Periph) ARLO 

func (p *I2C_Periph) ARLO() RMSR1

func (*I2C_Periph) BERR 

func (p *I2C_Periph) BERR() RMSR1

func (*I2C_Periph) BTF 

func (p *I2C_Periph) BTF() RMSR1

func (*I2C_Periph) BUSY 

func (p *I2C_Periph) BUSY() RMSR2

func (*I2C_Periph) BaseAddr 

func (p *I2C_Periph) BaseAddr() uintptr

func (*I2C_Periph) CCRVAL 

func (p *I2C_Periph) CCRVAL() RMCCR

func (*I2C_Periph) DMAEN 

func (p *I2C_Periph) DMAEN() RMCR2

func (*I2C_Periph) DUALF 

func (p *I2C_Periph) DUALF() RMSR2

func (*I2C_Periph) DUTY 

func (p *I2C_Periph) DUTY() RMCCR

func (*I2C_Periph) ENARP 

func (p *I2C_Periph) ENARP() RMCR1

func (*I2C_Periph) ENDUAL 

func (p *I2C_Periph) ENDUAL() RMOAR2

func (*I2C_Periph) ENGC 

func (p *I2C_Periph) ENGC() RMCR1

func (*I2C_Periph) ENPEC 

func (p *I2C_Periph) ENPEC() RMCR1

func (*I2C_Periph) FREQ 

func (p *I2C_Periph) FREQ() RMCR2

func (*I2C_Periph) FS 

func (p *I2C_Periph) FS() RMCCR

func (*I2C_Periph) GENCALL 

func (p *I2C_Periph) GENCALL() RMSR2

func (*I2C_Periph) ITBUFEN 

func (p *I2C_Periph) ITBUFEN() RMCR2

func (*I2C_Periph) ITERREN 

func (p *I2C_Periph) ITERREN() RMCR2

func (*I2C_Periph) ITEVTEN 

func (p *I2C_Periph) ITEVTEN() RMCR2

func (*I2C_Periph) LAST 

func (p *I2C_Periph) LAST() RMCR2

func (*I2C_Periph) MSL 

func (p *I2C_Periph) MSL() RMSR2

func (*I2C_Periph) NOSTRETCH 

func (p *I2C_Periph) NOSTRETCH() RMCR1

func (*I2C_Periph) OVR 

func (p *I2C_Periph) OVR() RMSR1

func (*I2C_Periph) PE 

func (p *I2C_Periph) PE() RMCR1

func (*I2C_Periph) PEC 

func (p *I2C_Periph) PEC() RMCR1

func (*I2C_Periph) PECERR 

func (p *I2C_Periph) PECERR() RMSR1

func (*I2C_Periph) PECVAL 

func (p *I2C_Periph) PECVAL() RMSR2

func (*I2C_Periph) POS 

func (p *I2C_Periph) POS() RMCR1

func (*I2C_Periph) RXNE 

func (p *I2C_Periph) RXNE() RMSR1

func (*I2C_Periph) SB 

func (p *I2C_Periph) SB() RMSR1

func (*I2C_Periph) SECADD1_7 

func (p *I2C_Periph) SECADD1_7() RMOAR2

func (*I2C_Periph) SMBALERT 

func (p *I2C_Periph) SMBALERT() RMSR1

func (*I2C_Periph) SMBDEFAULT 

func (p *I2C_Periph) SMBDEFAULT() RMSR2

func (*I2C_Periph) SMBHOST 

func (p *I2C_Periph) SMBHOST() RMSR2

func (*I2C_Periph) SMBTYPE 

func (p *I2C_Periph) SMBTYPE() RMCR1

func (*I2C_Periph) SMBUS 

func (p *I2C_Periph) SMBUS() RMCR1

func (*I2C_Periph) START 

func (p *I2C_Periph) START() RMCR1

func (*I2C_Periph) STOP 

func (p *I2C_Periph) STOP() RMCR1

func (*I2C_Periph) STOPF 

func (p *I2C_Periph) STOPF() RMSR1

func (*I2C_Periph) SWRST 

func (p *I2C_Periph) SWRST() RMCR1

func (*I2C_Periph) TIMEOUT 

func (p *I2C_Periph) TIMEOUT() RMSR1

func (*I2C_Periph) TRA 

func (p *I2C_Periph) TRA() RMSR2

func (*I2C_Periph) TXE 

func (p *I2C_Periph) TXE() RMSR1

type OAR1 

type OAR1 uint16
const (
	ADD1_7  OAR1 = 0x7F << 1  //+ Interface Address.
	ADD8_9  OAR1 = 0x03 << 8  //+ Interface Address.
	ADD0    OAR1 = 0x01 << 0  //+ Bit 0.
	ADD1    OAR1 = 0x01 << 1  //  Bit 1.
	ADD2    OAR1 = 0x02 << 1  //  Bit 2.
	ADD3    OAR1 = 0x04 << 1  //  Bit 3.
	ADD4    OAR1 = 0x08 << 1  //  Bit 4.
	ADD5    OAR1 = 0x10 << 1  //  Bit 5.
	ADD6    OAR1 = 0x20 << 1  //  Bit 6.
	ADD7    OAR1 = 0x40 << 1  //  Bit 7.
	ADD8    OAR1 = 0x01 << 8  //  Bit 8.
	ADD9    OAR1 = 0x02 << 8  //  Bit 9.
	ADDMODE OAR1 = 0x01 << 15 //+ Addressing Mode (Slave mode).
)

func (OAR1) Field 

func (b OAR1) Field(mask OAR1) int

func (OAR1) J 

func (mask OAR1) J(v int) OAR1

type OAR2 

type OAR2 uint16
const (
	ENDUAL    OAR2 = 0x01 << 0 //+ Dual addressing mode enable.
	SECADD1_7 OAR2 = 0x7F << 1 //+ Interface address.
)

func (OAR2) Field 

func (b OAR2) Field(mask OAR2) int

func (OAR2) J 

func (mask OAR2) J(v int) OAR2

type RCCR 

type RCCR struct{ mmio.U16 }

func (*RCCR) Bits 

func (r *RCCR) Bits(mask CCR) CCR

func (*RCCR) ClearBits 

func (r *RCCR) ClearBits(mask CCR)

func (*RCCR) Load 

func (r *RCCR) Load() CCR

func (*RCCR) SetBits 

func (r *RCCR) SetBits(mask CCR)

func (*RCCR) Store 

func (r *RCCR) Store(b CCR)

func (*RCCR) StoreBits 

func (r *RCCR) StoreBits(mask, b CCR)

type RCR1 

type RCR1 struct{ mmio.U16 }

func (*RCR1) Bits 

func (r *RCR1) Bits(mask CR1) CR1

func (*RCR1) ClearBits 

func (r *RCR1) ClearBits(mask CR1)

func (*RCR1) Load 

func (r *RCR1) Load() CR1

func (*RCR1) SetBits 

func (r *RCR1) SetBits(mask CR1)

func (*RCR1) Store 

func (r *RCR1) Store(b CR1)

func (*RCR1) StoreBits 

func (r *RCR1) StoreBits(mask, b CR1)

type RCR2 

type RCR2 struct{ mmio.U16 }

func (*RCR2) Bits 

func (r *RCR2) Bits(mask CR2) CR2

func (*RCR2) ClearBits 

func (r *RCR2) ClearBits(mask CR2)

func (*RCR2) Load 

func (r *RCR2) Load() CR2

func (*RCR2) SetBits 

func (r *RCR2) SetBits(mask CR2)

func (*RCR2) Store 

func (r *RCR2) Store(b CR2)

func (*RCR2) StoreBits 

func (r *RCR2) StoreBits(mask, b CR2)

type RDR 

type RDR struct{ mmio.U16 }

func (*RDR) Bits 

func (r *RDR) Bits(mask DR) DR

func (*RDR) ClearBits 

func (r *RDR) ClearBits(mask DR)

func (*RDR) Load 

func (r *RDR) Load() DR

func (*RDR) SetBits 

func (r *RDR) SetBits(mask DR)

func (*RDR) Store 

func (r *RDR) Store(b DR)

func (*RDR) StoreBits 

func (r *RDR) StoreBits(mask, b DR)

type RMCCR 

type RMCCR struct{ mmio.UM16 }

func (RMCCR) Load 

func (rm RMCCR) Load() CCR

func (RMCCR) Store 

func (rm RMCCR) Store(b CCR)

type RMCR1 

type RMCR1 struct{ mmio.UM16 }

func (RMCR1) Load 

func (rm RMCR1) Load() CR1

func (RMCR1) Store 

func (rm RMCR1) Store(b CR1)

type RMCR2 

type RMCR2 struct{ mmio.UM16 }

func (RMCR2) Load 

func (rm RMCR2) Load() CR2

func (RMCR2) Store 

func (rm RMCR2) Store(b CR2)

type RMDR 

type RMDR struct{ mmio.UM16 }

func (RMDR) Load 

func (rm RMDR) Load() DR

func (RMDR) Store 

func (rm RMDR) Store(b DR)

type RMOAR1 

type RMOAR1 struct{ mmio.UM16 }

func (RMOAR1) Load 

func (rm RMOAR1) Load() OAR1

func (RMOAR1) Store 

func (rm RMOAR1) Store(b OAR1)

type RMOAR2 

type RMOAR2 struct{ mmio.UM16 }

func (RMOAR2) Load 

func (rm RMOAR2) Load() OAR2

func (RMOAR2) Store 

func (rm RMOAR2) Store(b OAR2)

type RMSR1 

type RMSR1 struct{ mmio.UM16 }

func (RMSR1) Load 

func (rm RMSR1) Load() SR1

func (RMSR1) Store 

func (rm RMSR1) Store(b SR1)

type RMSR2 

type RMSR2 struct{ mmio.UM16 }

func (RMSR2) Load 

func (rm RMSR2) Load() SR2

func (RMSR2) Store 

func (rm RMSR2) Store(b SR2)

type RMTRISE 

type RMTRISE struct{ mmio.UM16 }

func (RMTRISE) Load 

func (rm RMTRISE) Load() TRISE

func (RMTRISE) Store 

func (rm RMTRISE) Store(b TRISE)

type ROAR1 

type ROAR1 struct{ mmio.U16 }

func (*ROAR1) Bits 

func (r *ROAR1) Bits(mask OAR1) OAR1

func (*ROAR1) ClearBits 

func (r *ROAR1) ClearBits(mask OAR1)

func (*ROAR1) Load 

func (r *ROAR1) Load() OAR1

func (*ROAR1) SetBits 

func (r *ROAR1) SetBits(mask OAR1)

func (*ROAR1) Store 

func (r *ROAR1) Store(b OAR1)

func (*ROAR1) StoreBits 

func (r *ROAR1) StoreBits(mask, b OAR1)

type ROAR2 

type ROAR2 struct{ mmio.U16 }

func (*ROAR2) Bits 

func (r *ROAR2) Bits(mask OAR2) OAR2

func (*ROAR2) ClearBits 

func (r *ROAR2) ClearBits(mask OAR2)

func (*ROAR2) Load 

func (r *ROAR2) Load() OAR2

func (*ROAR2) SetBits 

func (r *ROAR2) SetBits(mask OAR2)

func (*ROAR2) Store 

func (r *ROAR2) Store(b OAR2)

func (*ROAR2) StoreBits 

func (r *ROAR2) StoreBits(mask, b OAR2)

type RSR1 

type RSR1 struct{ mmio.U16 }

func (*RSR1) Bits 

func (r *RSR1) Bits(mask SR1) SR1

func (*RSR1) ClearBits 

func (r *RSR1) ClearBits(mask SR1)

func (*RSR1) Load 

func (r *RSR1) Load() SR1

func (*RSR1) SetBits 

func (r *RSR1) SetBits(mask SR1)

func (*RSR1) Store 

func (r *RSR1) Store(b SR1)

func (*RSR1) StoreBits 

func (r *RSR1) StoreBits(mask, b SR1)

type RSR2 

type RSR2 struct{ mmio.U16 }

func (*RSR2) Bits 

func (r *RSR2) Bits(mask SR2) SR2

func (*RSR2) ClearBits 

func (r *RSR2) ClearBits(mask SR2)

func (*RSR2) Load 

func (r *RSR2) Load() SR2

func (*RSR2) SetBits 

func (r *RSR2) SetBits(mask SR2)

func (*RSR2) Store 

func (r *RSR2) Store(b SR2)

func (*RSR2) StoreBits 

func (r *RSR2) StoreBits(mask, b SR2)

type RTRISE 

type RTRISE struct{ mmio.U16 }

func (*RTRISE) Bits 

func (r *RTRISE) Bits(mask TRISE) TRISE

func (*RTRISE) ClearBits 

func (r *RTRISE) ClearBits(mask TRISE)

func (*RTRISE) Load 

func (r *RTRISE) Load() TRISE

func (*RTRISE) SetBits 

func (r *RTRISE) SetBits(mask TRISE)

func (*RTRISE) Store 

func (r *RTRISE) Store(b TRISE)

func (*RTRISE) StoreBits 

func (r *RTRISE) StoreBits(mask, b TRISE)

type SR1 

type SR1 uint16
const (
	SB       SR1 = 0x01 << 0  //+ Start Bit (Master mode).
	ADDR     SR1 = 0x01 << 1  //+ Address sent (master mode)/matched (slave mode).
	BTF      SR1 = 0x01 << 2  //+ Byte Transfer Finished.
	ADD10    SR1 = 0x01 << 3  //+ 10-bit header sent (Master mode).
	STOPF    SR1 = 0x01 << 4  //+ Stop detection (Slave mode).
	RXNE     SR1 = 0x01 << 6  //+ Data Register not Empty (receivers).
	TXE      SR1 = 0x01 << 7  //+ Data Register Empty (transmitters).
	BERR     SR1 = 0x01 << 8  //+ Bus Error.
	ARLO     SR1 = 0x01 << 9  //+ Arbitration Lost (master mode).
	AF       SR1 = 0x01 << 10 //+ Acknowledge Failure.
	OVR      SR1 = 0x01 << 11 //+ Overrun/Underrun.
	PECERR   SR1 = 0x01 << 12 //+ PEC Error in reception.
	TIMEOUT  SR1 = 0x01 << 14 //+ Timeout or Tlow Error.
	SMBALERT SR1 = 0x01 << 15 //+ SMBus Alert.
)

func (SR1) Field 

func (b SR1) Field(mask SR1) int

func (SR1) J 

func (mask SR1) J(v int) SR1

type SR2 

type SR2 uint16
const (
	MSL        SR2 = 0x01 << 0 //+ Master/Slave.
	BUSY       SR2 = 0x01 << 1 //+ Bus Busy.
	TRA        SR2 = 0x01 << 2 //+ Transmitter/Receiver.
	GENCALL    SR2 = 0x01 << 4 //+ General Call Address (Slave mode).
	SMBDEFAULT SR2 = 0x01 << 5 //+ SMBus Device Default Address (Slave mode).
	SMBHOST    SR2 = 0x01 << 6 //+ SMBus Host Header (Slave mode).
	DUALF      SR2 = 0x01 << 7 //+ Dual Flag (Slave mode).
	PECVAL     SR2 = 0xFF << 8 //+ Packet Error Checking Register.
)

func (SR2) Field 

func (b SR2) Field(mask SR2) int

func (SR2) J 

func (mask SR2) J(v int) SR2

type TRISE 

type TRISE uint16

func (TRISE) Field 

func (b TRISE) Field(mask TRISE) int

func (TRISE) J 

func (mask TRISE) J(v int) TRISE

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